The present invention relates to a digital operational processor and, more particularly, to an apparatus adapted for operational processing of data with multiple memory accesses such as draw operation in a bit-mapped display.
The draw operation in a bit-mapped display basically includes data computation, which is termed "raster operation", between rectangular areas on a bit-mapped memory. Such raster operation can be realized by programming the procedure shown in a flow chart of FIG. 4A. In this flow chart, Dest. Data is an abbreviation for destination data. The number, of times of repeating the procedure shown in the flow chart is proportional to the dimensions of the rectangular area and reaches, for example, a value on the order of 10.sup.5 to 10.sup.6. In five instructions for each procedure of the repeated steps, there are included three memory access instructions, and the time required for the raster operation is determined by the memory access time.
In an attempt to increase the raster operation speed, each procedure of repeated steps is rendered executable with three instructions as shown in FIG. 4B by realizing a read-modify-write step through hardwaring the raster operation. In this procedure, the decision instruction (Loop End ?) for repetition is not related to the memory access. Therefore, when the memory write access and the decision instruction for repetition are executed in parallel, the decision instruction is included in the memory access time if the memory access is slower than the execution of the instruction. As the result, the processing time in the flow chart is determined merely by the memory access time alone while the time required for execution of the decision instruction is negligible, hence accomplishing a higher speed in the raster operation.
For achieving parallel execution of the memory write access and the operational process, there may be proposed a method by which the write address and the write data are latched in registers, and the processor executes the next instruction without waiting for completion of the write access. An exemplary system utilizing such idea is Am 29116 manufactured by Advanced Micro Devices Corporation.
Although the above-mentioned prior art successfully realizes a parallel execution of the data operation in the memory write mode, proper consideration is not given to a parallel execution in the memory read mode, and consequently there has been a problem heretofore with regard to speeding up more complicated data processing.